Recent development in three-dimensional (3D) chip stacking technology employs thin semiconductor chips to enable vertical stacking of multiple semiconductor chips. Since a typical semiconductor substrate as manufactured in a normal semiconductor processing sequence has a thickness from about 500 μm to about 1,000 μm, formation of through-wafer vias (TWVs) that extend through the entirety of the thickness of the semiconductor substrate requires extraordinary processing sequences and high processing cost. An alternative is to thin a semiconductor substrate after the formation of semiconductor devices and interconnects on a semiconductor substrate is completed and prior to dicing the semiconductor into semiconductor chips, or “dies.” By thinning the semiconductor substrate to a thickness less than 300 μm, through-wafer vias (TWVs) having a less height than the full thickness of the semiconductor substrate employed during a semiconductor manufacturing sequence may be employed to enable electrical connection between multiple semiconductor chips. In addition, thinned semiconductor substrate provides additional advantages such as improved thermal dissipation and improved device coupling across semiconductor devices located in different semiconductor chips that are vertically stacked.
Controlled Collapse Chip Connection (C4) packaging, which employs C4 balls each of which contacts a C4 pads on the semiconductor chip and another C4 pad on a packaging substrate, is employed in advanced semiconductor chips to accommodate a high number of input/output nodes, which may be up to 5,000. Each of these nodes is electrically connected to a C4 pad on a top surface of the semiconductor chip in a two dimensional array.
While desirable for enabling chip stacking with through-wafer vias (TWVs) having reduced thickness, thinning a semiconductor substrate containing C4 balls has achieved only limited success in the industry. FIGS. 1A-1D show a sequence of vertical cross-sectional views of a first exemplary prior art semiconductor structure.
Referring to FIG. 1A, a C4 semiconductor substrate includes a semiconductor substrate 110, an array of C4 pads 112, and an array of C4 balls 120. The semiconductor substrate 110 includes at least one semiconductor device and at least one metal interconnect structure that is connected to the array of C4 pads 112. The thickness of the semiconductor substrate 110, which is herein referred to as an “initial thickness” ti′, is typically from about 500 μm to about 1,000 μm, and typically depends on the diameter of the semiconductor substrate 110. The diameter of the C4 balls 120 is on the order of 100 μm.
Referring to FIG. 1B, a C4 grind tape 130, which comprises a tape adhesive layer 130A and a tape base layer 130B, is applied to the top surface of the semiconductor substrate 110 containing the C4 balls 120. The tape base layer 130B comprises a polymer material or a plastic material. The tape adhesive layer 130A comprises an ultraviolet (UV) sensitive adhesive material, which loses adhesive property upon exposure to ultraviolet light. For this reason, upon application of the C4 grind tape 130 onto the semiconductor substrate 10, the C4 grind tape 130 is kept away from exposure to ultraviolet light until thinning of the semiconductor substrate is completed. The thickness of the tape adhesive layer 130A is greater than the height of the C4 ball 120, which is on the order of 100 μm.
Referring to FIG. 1C, the semiconductor substrate 110 is thinned by polishing and/or grinding. The C4 grind tape 130 provides mechanical support for the semiconductor substrate 110 during the thinning process, which produces a thinned semiconductor substrate 110′. Since the C4 grind tape 130 is not a rigid structure and the thickness of the tape adhesive layer 130A typically exceeds 100 μm, support of the semiconductor substrate 110′ is not firm and the thinned semiconductor substrate 110′ is subject to various stress during handling of the assembly of the C4 grind tape 130 and the thinned semiconductor substrate 110′. For this reason, there is a limit to the thickness of the thinned semiconductor substrate 110′, which is herein referred to as a “final thickness” tf′. A practical lower limit on the final thickness tf′ is about 150 μm.
Referring to FIG. 1D, the C4 grind tape 130 is irradiated by ultraviolet light, which deactivates the oligamer in the tape adhesive layer 130A to remove cross-linking therein. The tape adhesive layer 130A thus loses adhesive property upon the ultraviolet irradiation. The C4 grind tape 130 is the peeled off the thinned semiconductor substrate 110′ and the C4 balls 120. While the final thickness tf′ is less than the initial thickness ti′, the mechanical characteristics of the tape adhesive layer 130A places a practical limitation on the final thickness tf′, i.e., the final thickness tf′ is greater than about 200 μm. When thinning of the semiconductor substrate 110 to a thickness less than about 200 μm, a substrate breakage readily occurs, rendering the thinning process commercially not viable.
An alternate scheme for thinning a semiconductor substrate containing wirebond pads instead of C4 balls is known in the art. FIGS. 2A-2G show a sequence of vertical cross-sectional views of a second exemplary prior art semiconductor structure.
Referring to FIG. 2A, a wirebond semiconductor substrate includes a semiconductor substrate 210 and an array of wirebond pads 214. The semiconductor substrate 210 includes at least one semiconductor device and at least one metal interconnect structure that is connected to the array of wirebond pads 214. The thickness of the semiconductor substrate 210, which is herein referred to as an “initial thickness” ti″, is typically from about 500 μm to about 1,000 μm, and typically depends on the diameter of the semiconductor substrate 210. The height of the wirebond pads 214 is on the order of 2 μm.
Referring to FIG. 2B, a deactivatable adhesive layer 230 is applied to the top surface of the semiconductor substrate 210 containing the wirebond pads 214. The deactivatable adhesive layer 230 comprises an adhesive material, which may be subsequently deactivated upon exposure to heat or chemical treatment. The thickness of the deactivatable adhesive layer 230 is typically from about 10 μm to about 20 μm.
Referring to FIG. 2C, a carrier substrate 240 is bonded to the deactivatable adhesive layer 230. The carrier substrate 240 comprises a solid material that provides structural support during subsequent thinning of the semiconductor substrate 210.
Referring to FIG. 2D, the semiconductor substrate 210 is thinned by polishing and/or grinding. The carrier substrate 240 provides mechanical support for the semiconductor substrate 210 during the thinning process, which produces a thinned semiconductor substrate 210′. The thickness of the thinned semiconductor substrate 210′, which is herein referred to as a “final thickness” tf″. The final thickness tf″ may be less than 50 μm.
Referring to FIG. 2E, the deactivatable adhesive layer 230 is deactivated to lose adhesive property by exposure to heat treatment or chemical treatment. In case heat treatment is employed, the temperature of the deactivatable adhesive layer 230 may be elevated up about 160° C. In case chemical treatment is employed, a chemical is employed to change the property of the deactivatable adhesive layer 230 by reaction. The deactivatable adhesive layer 230 may be porous to allow percolation of the chemical in this case. Upon deactivation, the deactivatable adhesive layer 230 becomes a deactivated layer 230′, which is substantially less adhesive than the deactivatable adhesive layer 230 prior to deactivation. The thermal cycling or the chemical treatment may have adverse impact on the thinned semiconductor substrate 210 through thermal, chemical, or structural degradation.
Referring to FIG. 2F, the carrier substrate 240 is removed from the deactivated layer 230′. Referring to FIG. 2G, the deactivated layer 230′ is delaminated from the thinned semiconductor layer 210′.
As far as C4 semiconductor substrates, i.e., semiconductor substrates having C4 balls which typically have a diameter about 100 μm, are concerned, the thickness of thinned semiconductor substrates is limited to a thickness greater than about 200 μm since the C4 grind tape 130 of FIG. 1B does not provide sufficient mechanical support during the thinning of the semiconductor substrate in the assembly of a C4 semiconductor substrate 110 and a C4 grind tape 130. In view of this, there exists a need for a method of thinning a C4 semiconductor substrate to a thickness less than about 200 μm without subjecting a thinned C4 semiconductor substrate to a significant risk of breakage.
As far as wirebond semiconductor substrates, i.e., semiconductor substrates have wirebond pads, are concerned, the thinned semiconductor substrate 210′ may be subjected to harmful thermal or chemical treatment, which is necessary to deactivate the deactivatable adhesive layer 230 and to form a deactivated layer 230′ therefrom but tends to damage the thinned semiconductor substrate thermally, structurally, and/or chemically. In view of this, there exists a need for a method of thinning a wirebond semiconductor substrate without subjecting a thinned wirebond semiconductor substrate to exposure to heat treatment or chemical treatment.